The present invention relates to a memory control system for a data processing system wherein operands are placed in the memory and fetched as occasion demands that they be executed, and in particular to a memory control system for a data processing system wherein it is allowed to place an operand in an arbitrary address and the length of the operand is allowed to exceed the unit length of processing in the execution unit. More particularly, the present invention is applied to a data processing system equipped with a so-called alignment mechanism whereby such an operand placed in an arbitrary address can be displaced to specified positions suited to the execution unit and then be fetched.
An example of data processing system equipped with an alignment mechanism is disclosed in Japanese Patent Application Laid-Open Publication No. 94133/78. Hereafter, the data processing systen is assumed to be equipped with an alignment mechanism wherein the address is the byte address, the unit length of the memory reference is 8 bytes and the maximum unit of processing in the execution unit is also 8 bytes. In this case, for deriving a desired operand at the first memory reference even if the operand is spread over an 8-byte boundary, i.e., over a boundary between adjacent 8-byte blocks, two consecutive 8-byte blocks are fetched by each memory reference. The 8-byte block refers to a continuous area composed of 8 bytes having the leading address which is a multiple of 8 and memory reference is effected on the unit of the 8-byte block. Since the unit of processing in the execution unit is 8 bytes, at least half of the 16-byte data which has been fetched must be discarded without being processed. In processing an instruction having a long operand exceeding 8 bytes, execution in the execution unit is effected for 8 bytes at a time while 16 bytes are fetched from the memory for the 8-byte data to be processed in the execution unit. Assuming that an address with a smaller value is referenced earlier, the reference address increments only by 8 bytes at a time. As a result, intermediate 8-byte blocks other than 8-byte blocks to which both ends of the operand belong are fetched twice.
FIG. 1 shows the schematic construction of an example of a memory control unit in a conventional data processing system having such an alignment mechanism. The memory illustrated in FIG. 1 is a buffer memory. The buffer memory is a memory having a smaller capacity and faster speed compared with the main memory which is not illustrated. The buffer memory holds a part of data held by the main memory. By placing data frequently used in the buffer memory, the execution unit can utilize data from the buffer memory rapidly. The unit of capacity placed in the buffer memory as the copy of contents in the main memory is 64 bytes specified by the address. In FIG. 1, numeral 1 denotes an address register for fetching an 8-byte block having an even address within the 64-byte block and numeral 2 denotes an address register for fetching an 8-byte block having an odd address within the 64-byte block. Numeral 3 is a memory for storing an 8-byte block having an even address within the 64-byte block and numeral 4 is a memory for storing an 8-byte block having an odd address within the 64-byte block. The address registers 1 and 2 are connected to memories 3 and 4 respectively by address lines 8 and 9. Numerals 5 and 6 are data registers for storing 8-byte data each which have been fetched respectively from the memories 3 and 4. The data registers 5 and 6 are connected to the memories 3 and 4 respectively by data lines 10 and 11. The data lines 10 and 11 may also serve to transfer the data which has been fetched in memory reference excepting operand fetch toward another register or the like. However, destinations of the data lines 10 and 11 for the just described purpose are omitted in FIG. 1. Numeral 7 denotes an aligner for moving a desired operand within the memory data which has been stored in the data registers 5 and 6 to render it left justified or right justified. The aligner 7 is connected to the data registers 5 and 6 via data lines 12 and 13. The operand aligned by the aligner 7 or a part thereof is sent out to the execution unit via a data line 14. Numeral 15 denotes a memory address generator having an operand address line 16 as its input and memory address lines 17 and 18 as its output. The memory address generator 15 functions to generate a memory address for an 8-byte block indicated by an operand fetch address on the operand address line 16 and a memory address for the next 8-byte block and to send out the even memory address onto the memory address line 17 and the odd memory address onto the memory address line 18. The memory address lines 17 and 18 are respectively connected to address registers 1 and 2. For the conventional data processing system having the alignment mechanism as illustrated in FIG. 1, processing for an operand which is spread over an 8-byte boundary will be described referring to FIG. 2.
In FIG. 2a, the shaded region represents an operand composed of 40 bytes in the memory. This memory is divided into blocks respectively composed of 64 bytes. The above described operand starts half-way on the first 8-byte block within this 64-byte block and ends in the middle of the sixth 8-byte block. In FIG. 2a, addresses 0 to 7 within the 64-byte block are assigned to respective 8-byte blocks. Denoting an 8-byte block having an address within the 64-byte block of 0 by 8-byte block 0, an 8-byte block having the address within the 64-byte block of 1 by 8-byte block 1, an 8-byte block having the address within the 64-byte block of 2 of 8-byte block 2, - - -, and an 8-byte block having the address within the 64-byte block of 7 by 8-byte block 7, the shaded 40-byte operand starts at the center of 8-byte block 0 and ends at the center of the 8-byte block 5.
In the conventional data processing system having an alignment mechanism, this operand is fetched in five steps as illustrated in FIG. 2b. In FIG. 2b, said 64-byte block and two data registers 5 and 6 for storing 8-byte data fetched from the memory are illustrated for each step. To be readily understandable, 8-byte blocks having an even address within said 64-byte block are piled up vertically in the left half of the 64-byte block and are stored in the memory 3, 8-byte blocks having an odd address are piled up vertically in the right half and are stored in the memory 4 and only the 8-byte blocks under notice are enclosed by frames and provided with addresses within the 64-byte block. At first in the step (1), for sending out the eight leftmost bytes of said operand to the execution unit, 8-byte blocks 0 and 1 of said 64-byte block are fetched respectively from the memories 3 and 4 and are stored into data registers 5 and 6, respectively. The desired 8-byte data (A and B) is stored in the middle of these data registers 5 and 6 as shaded in FIG. 2b. The contents of these data registers 5 and 6 are left justified by the aligner 7 illustrated in FIG. 1 and are sent out to the execution unit. In step (2), for sending out eight bytes ranging from the ninth byte when counted from the leftmost end of the operand until sixteenth byte toward the execution unit, 8-byte blocks 1 and 2 are fetched to be stored into the data registers 5 and 6. The desired 8-byte data (C and D) is stored in both ends of these data registers 5 and 6 as shaded in FIG. 2b. The contents of these data registers are subjected to cyclic shift in the aligner 7 to be left justified and are sent out to the execution unit. The similar procedures are repeated and said operand composed of A to J is completely sent out to the execution unit in a total of five steps. As evident from the above description, all of the intermediate 8-byte blocks 1 to 4 are fetched twice while 8-byte blocks 0 and 5 at the ends of the operand are fetched only once. In fetching the intermediate 8-byte blocks 1 to 4 twice, only a part of the data which has been fetched is sent out to the execution unit and the remaining part is discarded.
As described above, in the conventional data processing system having an alignment mechanism, the same memory area is referenced twice when a long operand is to be fetched. Accordingly, the average amount of memory reference per instruction is large as compared with the data processing system having no alignment mechanism. Therefore, the performance per unit memory throughput might be inferior in the data processing system having an alignment mechanism.
A memory is usually divided into blocks respectively composed of 32 to 128 bytes. In the above example, the block is composed of 64 bytes. If an operand is spread over two blocks, data in two blocks must be fetched separately. Fetch processing of such an operand which is spread over a boundary between blocks will be hereafter referred to as BX (Block Cross) processing. When the necessity of BX processing is brought about in the conventional data processing system, a memory reference must be effected twice. Accordingly, in a program wherein the BX processing is frequently used, the average amount of memory reference is increased. In addition, an extra time is consumed for effecting the memory reference twice. Thus, the BX processing is one of the causes of performance deterioration. This situation will be described referring to an example illustrated in FIG. 3.
The shaded region in FIG. 3a is an operand which is 40 bytes long and is spread over a boundary between 64-byte blocks. As illustrated in FIG. 3b, this operand is fetched in six steps. In steps (1) and (2), the first 8-bytes (A and B) when the operand is divided at intervals of eight bytes into six sections and the second eight bytes (C and D) are respectively fetched. The details are similar as those in FIG. 2b and hence will not be described. The third 8 bytes of the operand are spread over the boundary between 64-byte blocks and are fetched in two steps (3) and (4). That is to say, the 8-byte block 7 within the 64-byte block to which the left half (E) of the third 8 bytes of the operand belongs is fetched into the data register 6. The desired data (E) shaded in FIG. 3b is aligned by the aligner 7. Subsequently in step (4), 8-byte block 0' within the 64-byte block to which the right half (F) of the third eight bytes of the operand belongs is fetched into the data register 5. For discriminating from 8-byte blocks within the 64-byte block to which the left half of the operand belongs, the address of an 8-byte block within the 64-byte block to which the right half of the operand belongs is provided with "'". The desired data shaded in FIG. 3b is aligned by the aligner 7 and then coupled with the data which has been already aligned in the step (3). The coupled data is sent out to the execution unit. The coupling process is not illustrated. In subsequent steps (5) and (6), the remaining fourth 8 bytes (G and H) and fifth 8 bytes (I and J) are fetched, thereby the operand composed of (A) to (J) which is 40 bytes long having been entirely fetched.
As it will be seen from the above explanation, the BX processing for fetching the third 8 bytes (E and F) requires two steps (3) and (4). In addition, it should be considered that memory reference of 16 bytes is effected for each of the steps (3) and (4). As a result, in the BX processing for obtaining eight bytes within the operand, a memory reference for 32 bytes is required.
On the other hand, in the case where the memory is divided into blocks respectively composed of 64 bytes in the conventional memory control unit is illustrated in FIG. 1, the memory address generator 15 functions as follows. That is to say, the memory address generator 15 generates the memory address of the 8-byte block specified by the operand fetch address on the operand address line 16 and the memory address of the 8-byte block succeeding said 8-byte block and then sends out an even memory address among them onto the memory address line 17 and an odd memory address among them onto the memory address line 18. In the case where the operand fetch address specified by the operand address line 16 corresponds to the last 8-byte block within the 64-byte block, i.e., 8-byte block 7, however, it is generally impossible to generate the buffer address of the succeeding 8-byte block.
As heretofore described, the BX processing in the conventional data processing system always requires a memory reference twice and in addition requires a larger amount of memory reference as compared with the usual operand fetch wherein the BX processing is unnecessary. They are also causes of performance deterioration in the data processing system.